1. Field of the Invention
The present invention relates to a dead time control circuit used in a predriver for driving a half bridge circuit or a push-pull type output buffer for driving a load.
2. Description of the Related Art
In a push-pull type output buffer, two switching elements are connected between a power supply terminal and a ground terminal. When the switching elements are alternately turned ON and OFF to drive a load connected thereto, if the switching elements are simultaneously turned ON, a large penetration current flows through the push-pull type output buffer, so that the switching elements would be broken down.
In order to avoid such a large penetration current, a simultaneous-OFF time or a dead time is introduced between the ON times of the switching elements. Generally, two dead time control circuits each corresponding to one of the switching elements are provided.
A first prior art dead time control circuit is constructed by a delay circuit formed by two inverters connected in series for delaying an input signal and an AND circuit for receiving the input signal via the delay circuit and directly. This will be explained later in detail.
In the above-described first prior art dead time control circuit, however, even when the delay time of the delay circuit fluctuates due to environmental factors such as temperature, power supply voltage, etc., it is impossible to adjust the delay time, i.e., the dead time.
A second prior art dead time control circuit further includes a delay circuit formed by an external resistor and an external capacitor between the inverters of the first prior art dead time control circuit. Therefore, when the delay time fluctuates due to environmental factors, the delay time can be adjusted by the external resistor and the external capacitor. This also will be explained later in detail.
The above-described second prior art dead time control circuit, however, is increased in size and manufacturing cost due to the external resistor and the external capacitor. Also, since the characteristics of the external resistor and the external capacitor per se fluctuate, it is impossible to accurately control the dead time.
A third prior art dead time control circuit further includes two constant current sources connected to one of the inverters of the first prior art dead time control circuit, the constant current source including analogous circuit elements as in the other of the inverters. As a result, the response speed characteristic of one of the inverters is opposite to that of the other, so that the entire delay time of the dead time control circuit becomes stable. This also will be explained later in detail.